At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara last week, Samsung unveiled three new memory and storage architectures aimed squarely at the AI infrastructure bottleneck. The most striking of the three — zHBM — rethinks where memory lives in a system entirely.
The Core Problem zHBM Solves
High Bandwidth Memory (HBM) is the memory type used in today's AI accelerators: the H100, the MI300X, and their successors. The standard arrangement places HBM beside the GPU die, connected via a silicon interposer. That works, but the interposer consumes physical space and imposes bandwidth limits. As AI models grow, those limits are becoming a genuine constraint on what hardware can do.
zHBM takes a different approach: it stacks memory directly above the AI accelerator, using advanced wafer bonding to integrate the two dies vertically. Samsung projects zHBM will deliver approximately 8× the performance of HBM5 and more than 10× the memory density. Those aren't incremental numbers. If the projections hold through actual productization, zHBM represents a step-change in what an AI chip can do with local memory.
The Other Two Technologies
Samsung also introduced zNAND-O, a next-generation NAND architecture built for edge AI environments. It comes in four- and eight-layer configurations, targeting real-time, data-intensive applications where latency matters as much as throughput. Edge AI inference — running models on devices rather than in data centers — is an increasingly important market, and zNAND-O is aimed directly at it.
The third announcement was V10 BV-NAND, the industry's first 400-plus-layer NAND enabled by wafer bonding. The wafer bonding technique separates the array and peripheral circuits onto different wafers before bonding them together, which is what makes 400+ layers achievable. V10 BV-NAND increases storage density by roughly 58% over Samsung's previous V9 generation.
All three technologies share the same foundational ingredient: wafer bonding. It's a manufacturing technique that joins two separately fabricated wafers at the die level, and it's what lets Samsung push density and performance in ways that traditional stacking approaches can't.
When Does This Ship?
Samsung positioned all three as roadmap items, not products you can order today. zHBM and zNAND-O are concept architectures; V10 BV-NAND is further along but still pre-production. The FMS presentation laid out the memory roadmap through HBM4E and HBM5, situating these technologies in the longer arc of AI infrastructure scaling.
What matters now is that the architectural direction is public and specific. Competitors are watching, and the wafer bonding approach will likely force responses across the industry. The memory wall — the gap between processor speed and memory bandwidth — has been the defining hardware problem of the AI era. Samsung just showed one direction for breaching it.